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Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B420F2048GM64 /SDIO /CFGPRESETVAL0

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Interpret as CFGPRESETVAL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INITSDCLKFREQ0 (INITCLKGENEN)INITCLKGENEN 0INITDRVST 0DSPSDCLKFREQ0 (DSPCLKGENEN)DSPCLKGENEN 0DSPDRVST

Description

Core Configuration Preset Value 0

Fields

INITSDCLKFREQ

Initial SD_CLK Frequency
INITCLKGENEN

Initial Clock Gen Enable
INITDRVST

Initial Drive Strength
DSPSDCLKFREQ

Preset Value for Default Speed of SD_CLK
DSPCLKGENEN

Default Speed Clock Gen Enable
DSPDRVST

Default Speed Drive Strength

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data